10M02DCV36I7G Programmable IC Chip
Field Programmable Gate Array (FPGA) IC 27 110592 2000 Package 36-UFBGA

The VCO frequency reported by the Intel Quartus Prime sotware in the PlL. summary section of the compilation report takes intoconsideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be loweithan the fvco specification.
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock sourcewhich is less than 200 ps.
Peak-to-peak jitter with a probability level of 10-12 (14 sigma, 99.99999999974404% confidence level). The output jiter specificationapplies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.

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