Features
• Dual-core architecture
– Two TMS320C28x 32-bit CPUs
– 200 MHz
– IEEE 754 single-precision Floating-Point Unit
(FPU)
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
• Two programmable Control Law Accelerators
(CLAs)
– 200 MHz
– IEEE 754 single-precision floating-point
instructions
– Executes code independently of main CPU
• On-chip memory
– 512KB (256KW) or 1MB (512KW) of flash
(ECC-protected)
– 172KB (86KW) or 204KB (102KW) of RAM
(ECC-protected or parity-protected)
– Dual-zone security supporting third-party
development
– Unique identification number
• Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator
– Windowed watchdog timer module
– Missing clock detection circuitry
• 1.2-V core, 3.3-V I/O design
• System peripherals
– Two External Memory Interfaces (EMIFs) with
ASRAM and SDRAM support
– Dual 6-channel Direct Memory Access (DMA)
controllers
– Up to 169 individually programmable,
multiplexed General-Purpose Input/Output
(GPIO) pins with input filtering
– Expanded Peripheral Interrupt controller (ePIE)
– Multiple Low-Power Mode (LPM) support with
external wakeup